Energy-effective issue logic

Energy-Effective Instruction Fetch Unit for Wide Issue Processors

Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instru...

Speculative Issue Logic

In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than one instruction per each cycle. The amount of instruction level parallelism will become more and more important when superscalar issue width is increased. With hardware support, instructions can be speculatively wake...

Effective Logic Computation

Energy-efficient issue queue design

The out-of-order issue queue (IQ), used in modern superscalar processors is a considerable source of energy dissipation. We consider design alternatives that result in significant reductions in the power dissipation of the IQ (by as much as 75%) through the use of comparators that dissipate energy mainly on a tag match, 0-B encoding of operands to imply the presence of bytes with all zeros and,...

The Weighting Issue in Fuzzy Logic

The objective of this paper is to establish a class of models for solving the weight problem in fuzzy logic. First, some constraints that weighted fuzzy logic should satisfy are given based on Triangular norms and conorms. Then, based on these constraints, a class of models (referred to as relative weighted models) are established for handling weights in fuzzy logic. These models are novel in t...